Semiconductor device and manufacturing method therefor

ABSTRACT

A ferroelectric capacitor having a bottom electrode ( 9   a ), a ferroelectric film ( 10   a ) and a top electrode ( 11   a ) is formed above a semiconductor substrate ( 1 ). The ferroelectric film ( 10   a ) is constituted of CSPZT with 0.1-5 mol % of La and 0.1-5 mol % of Nb.

TECHNICAL FIELD

The present invention relates to a semiconductor device suitable for anonvolatile memory having a ferroelectric capacitor, and a manufacturingmethod therefor.

BACKGROUND ART

With the development of digital technologies, there is an increasingtrend of high-speed processing or preservation of a large capacity data.Because of this, large-scale integration and high performance arerequired in semiconductor devices for use in electronic equipments.

Accordingly, to realize large-scale integration of a semiconductormemory device (DRAM), extensive studies and development are carried outon the techniques using a ferroelectric material or a high-permittivitymaterial, in place of a silicon oxide or a silicon nitride, as acapacitor insulating film for a capacitance element constituting theDRAM.

Also, to realize a nonvolatile RAM capable of performing high-speedwrite/read operation at a low voltage, studies and development are beingconducted actively in regard to a ferroelectric memory (FeRAM) using aferroelectric film having a spontaneous polarization characteristic, asa capacitor insulating film.

The ferroelectric memory (FeRAM) stores information utilizing ahysteresis characteristic of a ferroelectric substance. Theferroelectric memory includes in each memory cell a ferroelectriccapacitor having a ferroelectric film, as a capacitor dielectric filmdisposed between a pair of electrodes. In the ferroelectric substance,polarization occurs depending on a voltage applied between theelectrodes, and spontaneous polarization remains even after the appliedvoltage is removed. Also, when the polarity of the applied voltage isreversed, the polarity of the spontaneous polarization is also reversed.Therefore, information can be read out by detecting the spontaneouspolarization. Further, as compared with a flash memory, theferroelectric memory is operable at a low voltage, and capable ofhigh-speed writing with reduced power.

The ferroelectric film of the ferroelectric capacitor is formed of aPZT-based material, such as lead zirconate titanate (PZT) and La-dopedPZT (PLZT), a compound having a bismuth layer structured ferroelectrics,such as SrBi₂Ta₂O₉ (SBT,Y1) and SrBi₂(Ta,Nb) ₂O₉ (SBTN,YZ)Conventionally, as a film-forming method of the ferroelectric film,there has been used a sol-gel method, a sputtering method or an MOCVDmethod. By means of such the film-forming method, a ferroelectric filmof an amorphous phase is formed on a bottom electrode film, andthereafter, the ferroelectric film is crystallized to a crystal ofperovskite structure by a thermal treatment. A crystallinity of theferroelectric film is subject to a crystallinity of the bottom electrodefilm, the film-forming condition and the crystallization condition ofthe ferroelectric film, and the like. Therefore, conventionally, byadjusting such the conditions, it has been intended to improve thecrystallinity of the ferroelectric film. However, in recent years, ithas become unable to satisfy the requirements of further improvement onthe crystallinity. As a result, a ferroelectric capacitor havingsufficient characteristics cannot be obtained any more, nor variation inthe performance of the memory cell in an identical chip can besuppressed sufficiently.

Also, for example, in Patent document 1 (Japanese Patent ApplicationLaid-open No. 2003-2647), there is disclosed the adoption of a varietyof compositions of ferroelectric films for the purpose of decreasing acrystallization temperature of the ferroelectric film. However, there isno such method that can obtain sufficient crystallinity.

Patent document 1: Japanese Patent Application Laid-open No. 2003-2647

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductordevice and a manufacturing method therefor, capable of obtaining a moreuniform and better characteristic.

The present invention is aimed at a semiconductor device including asemiconductor substrate and a ferroelectric capacitor with aferroelectric film formed above the semiconductor substrate. Accordingto the present invention, the ferroelectric film is constituted of asubstance of which chemical formula is expressed by ABO₃, added with Laand Nb.

Also, in a manufacturing method of a semiconductor device according tothe present invention, a ferroelectric capacitor with a ferroelectricfilm is formed above a semiconductor substrate. At this time, a film isformed as the ferroelectric film, which film is constituted of asubstance of which chemical formula is expressed by ABO₃, added with Laand Nb.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a circuit diagram showing a memory cell array structure ofa ferroelectric memory (semiconductor device) to be manufactured by amethod according to an embodiment of the present invention.

FIG. 2A shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order, according to theembodiment of the present invention.

FIG. 2B shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2A, according to the embodiment of the present invention.

FIG. 2C shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2B, according to the embodiment of the present invention.

FIG. 2D shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2C, according to the embodiment of the present invention.

FIG. 2E shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2D, according to the embodiment of the present invention.

FIG. 2F shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2E, according to the embodiment of the present invention.

FIG. 2G shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2F, according to the embodiment of the present invention.

FIG. 2H shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2G, according to the embodiment of the present invention.

FIG. 2I shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2H, according to the embodiment of the present invention.

FIG. 2J shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2I, according to the embodiment of the present invention.

FIG. 2K shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2J, according to the embodiment of the present invention.

FIG. 2L shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2K, according to the embodiment of the present invention.

FIG. 2M shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2L, according to the embodiment of the present invention.

FIG. 2N shows a cross sectional view illustrating the manufacturingmethod of a ferroelectric memory in process order subsequently to FIG.2M, according to the embodiment of the present invention.

FIG. 3 shows a graph illustrating examination results of an in-planeorientation distribution and crystallinity.

FIG. 4A shows a graph illustrating an examination result of a nonlinearcapacity.

FIG. 4B shows a graph illustrating an examination result of anelectrostatic capacity.

FIG. 5A shows a graph illustrating an examination result of a value P.

FIG. 5B shows a graph illustrating an examination result of a value U.

FIG. 6 shows a graph illustrating an examination result of a switchingcharge Q_(SW).

FIG. 7 shows a graph illustrating an examination result of a coercivevoltage V_(C).

FIG. 8 shows a graph illustrating an examination result of a leakcurrent.

FIG. 9A shows a graph illustrating examination results of a switchingcharge Q_(SW) and a difference (P−U) (discrete).

FIG. 9B shows a graph illustrating examination results of a switchingcharge Q_(SW) and a difference (P−U) (memory cell array).

FIG. 10A shows a graph illustrating an examination result of a leakcurrent (discrete).

FIG. 10B shows a graph illustrating a examination result of a leakcurrent (memory cell array).

FIG. 11 shows a graph illustrating a relationship between an appliedvoltage and a switching charge Q_(SW).

FIG. 12 shows a graph illustrating an examination result of a fatigueloss.

FIG. 13 shows a graph illustrating an examination result of a thermaldepolarization.

FIG. 14A shows a graph illustrating a relationship between a heattreatment time and a value (P−U).

FIG. 14B shows a graph illustrating an OS_RATE.

FIG. 15 shows a graph illustrating a relationship between an appliedvoltage and a polarization.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present invention will be describedconcretely, referring to the accompanying drawings. FIG. 1 is a circuitdiagram showing a memory cell array structure of a ferroelectric memory(semiconductor device) to be manufactured by a method according to theembodiment of the present invention.

In the memory cell array, there are provided a plurality of bit lines103 extending in one direction, a plurality of word lines 104 and platelines 105 extending in the direction perpendicular to the extendingdirection of the bit lines 103. Also, a plurality of memory cells of theferroelectric memory according to the present embodiment is disposed inan array form so as to be matched with a grid consisting of the bitlines 103, word lines 104 and plate lines 105. In each memory cell, aferroelectric capacitor (memory portion) 101 and a MOS transistor(switching portion) 102 are provided.

The gate of the MOS transistor 102 is connected to the word line 104.Also, one of the source and drain of the MOS transistor 102 is connectedto the bit line 103, while the other of the source and drain isconnected to one electrode of the ferroelectric capacitor 101. Further,the other electrode of the ferroelectric capacitor 101 is connected tothe plate line 105. Here, each word line 104 and each plate line 105 areshared by a plurality of MOS transistors 102 being aligned in the samedirection as the extending direction thereof. Similarly, each bit line103 is shared by the plurality of MOS transistors 102 being aligned inthe same direction as the extending direction thereof. The extendingdirection of the word line 104 and the plate line 105 and the extendingdirection of the bit line 103 may be referred to as a row direction anda column direction, respectively, in some cases. However, thearrangement of the bit line 103, the word line 104 and the plate line105 is not limited to the aforementioned one.

In the memory cell array of the ferroelectric memory thus constituted,data is stored according to the polarization state of the ferroelectricfilm provided in the ferroelectric capacitor 101.

Next, an embodiment of the present invention will be described. Here,for the sake of convenience, the cross sectional structure of eachmemory cell in the ferroelectric memory will be described together witha manufacturing method therefor. FIGS. 2A through 2N show cross sectionsillustrating a manufacturing method of the ferroelectric memory(semiconductor device) according to the embodiment of the presentinvention, shown in the process order.

In the present embodiment, first, as shown in FIG. 2A, an elementisolation insulating film 2 partitioning an element activating region isformed on the surface of a semiconductor substrate 1, such as a Sisubstrate, by a LOCOS (local oxidation of Silicon) method, for example.Next, in the element activating region partitioned by the elementisolation insulating film 2, there is formed a transistor (MOSFET)having a gate insulating film 3, a gate electrode 4, a silicide layer 5,a side wall 6 and source/drain diffusion layers constituted of alow-density diffusion layer 21 and a high-density diffusion layer 22. Asthe gate insulating film 3, for example, an SiO₂ film having a thicknessof the order of 100 nm is formed by thermal oxidation, for example.Then, a silicon oxynitride film 7 is formed over the entire surface tocover the MOSFET, and further, a silicon oxide film 8 a is formed overthe entire surface. The silicon oxynitride film 7 is formed for thepurpose of preventing hydrogen degradation of the gate insulating film 3and the like, when the silicon oxide film 8 a is formed. As the siliconoxide film 8 a, a TEOS (tetraethylorthosilicate) film having a thicknessof about 700 nm is formed by a CVD method, for example.

Thereafter, by performing an annealing process at 650° C. for 30 minutesin an N₂ atmosphere, degasification of the silicon oxide film 8 a isperformed. Next, as a bottom electrode adhesion layer, an Al₂O₃ film 8 bhaving a thickness of about 20 nm is formed on the silicon oxide film 8a by a sputtering method, for example. Here, as the bottom electrodeadhesion layer, it may also be possible to form a Ti film, a TiO_(x)film or the like having a thickness of about 20 nm. Subsequently, abottom electrode film 9 is formed on the Al₂O₃ film 8 b. As the bottomelectrode film 9, a Pt film having a thickness of about 150 nm is formedby a sputtering method, for example.

Next, as shown in FIG. 2B, a ferroelectric film 10 constituted of asubstance of which chemical formula is expressed as ABO₃ is formed onthe bottom electrode film 9 in an amorphous state. As the ferroelectricfilm 10, a (Pb,Ca,Sr,La)(Zr,Ti)O₃ film having a thickness of about100-200 nm is formed, for example, using a (Pb,Ca,Sr,La)(Zr,Ti)O₃ targetwhich includes 0.1-5 mol % of Nb and 0.1-5 mol % of La by an RFsputtering method. The above ferroelectric film 10 includes 0.1-5 mol %of Nb and 0.1-5 mol % of La. Nb is disposed on the B-site of thesubstance expressed by ABO₃ as a donor element, while La is disposed onthe A-site as a donor element. Next, in the atmosphere including Ar andO₂, thermal treatment (RTA: rapid thermal annealing) of not higher than600° C. is performed. As a result, the ferroelectric film 10 becomescrystallized, and also the Pt film constituting the bottom electrodefilm 9 is densified, and thereby mutual diffusion between Pt and O inthe vicinity of the boundary surface between the bottom electrode film 9and the ferroelectric film 10 is suppressed.

Thereafter, as shown in FIG. 2C, a top electrode film 11 is formed onthe ferroelectric film 10. When the top electrode film 11 is formed, forexample, after an IrO_(x) (1<x<2, for example, x=1.4) film (not shown)is formed having a thickness of about 50 nm by a sputtering method, forexample, thermal treatment (RTA) is performed, and further, an IrO₂ film(not shown) is formed. As a result of the thermal treatment afterforming the IrO_(x) (1<x<2, for example, x=1.4) film, the ferroelectricfilm 10 is completely crystallized.

Subsequently, after back surface cleaning is completed, the topelectrode 11 a is formed by patterning the top electrode film 11, asshown in FIG. 2D. Next, in an O₂ atmosphere, a recovery annealingprocess is performed at 650° C. for 60 minutes. The purpose of thethermal treatment is to recover physical damage and the like in theferroelectric film 10 when the top electrode 11 a is formed.

Thereafter, as shown in FIG. 2E, a capacitor insulating film 10 a isformed by patterning the ferroelectric film 10. Subsequently, oxygenannealing is performed to prevent an Al₂O₃ film to be formed later frombeing peeled off.

Next, as shown in FIG. 2F, an Al₂O₃ film 12 is formed over the entiresurface as a protective film by a sputtering method. Then, oxygenannealing is performed to alleviate the damage produced during thesputtering. The protective film (Al₂O₃ film 12) enables prevention ofhydrogen from penetrating into the ferroelectric capacitor from theoutside.

Thereafter, as shown in FIG. 2G, a bottom electrode 9 a is formed bypatterning of the Al₂O₃ film 12 and the bottom electrode film 9.Subsequently, oxygen annealing is performed to prevent another Al₂O₃film to be formed later peeling of.

Next, as shown in FIG. 2H, an Al₂O₃ film 13 is formed over the entiresurface as a protective film by a sputtering method. Then, oxygenannealing is performed to reduce a capacitor leak.

Thereafter, as shown in FIG. 2I, an interlayer insulating film 14 isformed over the entire surface by a high-density plasma method. Theinterlayer insulating film 14 has a thickness of about 1.5 μm, forexample.

Subsequently, as shown in FIG. 2J, by a CMP (chemical mechanicalpolishing) method, the interlayer insulating film 14 is planarized.Next, a plasma process is performed by use of a N₂O gas. As a result,the surface layer portion of the interlayer insulating film 14 isnitrided to some extent, making moisture hard to penetrate insidethereof. Here, the above plasma process is effective when a gasincluding at least one of N or O is used. Then, a hole reaching thehigh-density diffusion layer 22 of the transistor is formed through theinterlayer insulating film 14, the Al₂O₃ film 13, the Al₂O₃ film 8 b,the silicon oxide film 8 a and the silicon oxynitride film 7.Thereafter, by forming a Ti film and a TiN film consecutively inside thehole by a sputtering method, a barrier metal film (not shown) is formed.Subsequently, a W (tungsten) film is embedded into the hole by ma CVD(chemical vapor deposition) method, and the W film is planarized by aCMP method, so that a W plug 15 is formed.

Next, as shown in FIG. 2K, as an antioxidation film for the W plug 15,an SiON film 16 is formed by a plasma-enhanced CVD method, for example.

Then, as shown in FIG. 2L, a hole reaching the top electrode 11 a and ahole reaching the bottom electrode 9 a are formed through the SiON film16, the interlayer insulating film 14, the Al₂O₃ film 13 and the Al₂O₃film 12. Thereafter, oxygen annealing is performed for damage recovery.

Subsequently, as shown in FIG. 2M, the SiON film 16 is removed over theentire surface by etch-back, so that the surface of the W plug 15 isexposed. Next, as shown in FIG. 2N, in a state that a portion of thesurface of the top electrode 11 a, a portion of the surface of thebottom electrode 9 a, and the surface of the W plug 15 are exposed, anAl film is formed, and by patterning the Al film, Al wirings 17 areformed. At this time, for example, the W plug 15 is connected to the topelectrode 11 a or the bottom electrode 9 a, by use of a portion of theAl wirings 17.

Thereafter, further, the formations of the interlayer insulating filmand a contact plug, as well as wirings of the second layer from thebottom and succeeding layers and the like are performed. Then, a coverfilm is formed constituted of, for example, a TEOS oxidized film and aSiN film, so that a ferroelectric memory having a ferroelectriccapacitor is completed.

According to the present embodiment, as described above, theferroelectric film 10 including 0.1-5 mol % of Nb and 0.1-5 mol % of Lais formed. The ferroelectric film 10 having such a composition canimprove the in-plane orientation distribution and the crystallinity ofthe ferroelectric film 11 formed thereon. Accordingly, it becomespossible to suppress a coercive voltage and a leak current to lowvalues, while obtaining a high switching charge Q_(SW).

Now, test results having actually been performed by the inventor of thepresent invention will be described next.

(First Test)

In a first test, there were formed ferroelectric capacitors each havinga square plane shape with side lengths of 50 μm, and the in-planeorientation distribution of the ferroelectric films therein, acrystallinity, and electric characteristics (nonlinear capacity,electrostatic capacity, switching charge Q_(SW), coercive voltage V_(C),leak current and the like) were examined. As the ferroelectric films,(Pb,Ca,Sr)(Zr,Ti)O₃ films added with La and Nb were formed. The contents(mol %) of La and Nb in the ferroelectric film of each specimen and eachferroelectric film thickness (nm) are shown in Table 1.

TABLE 1 Specimens No. 1 No. 2 No. 3 No. 4 No. 5 No. 6 No. 7 No. 8 La 3 31.5 1.5 1.5 1.5 1.5 1.5 Nb 0 0 0 0 1 1 4 4 Thickness 150 120 150 120 150120 150 120

In FIG. 3, the examination results of the in-plane orientationdistribution and the crystallinity are shown. In the examination, byforming the ferroelectric film and forming an IrO_(x) film having athickness of 50 nm by a sputtering method thereon, and after performingRTA (thermal treatment) for 90 seconds, the crystallinity of eachspecimen was measured by a four-axis X-ray diffraction method. The FWHM(Full Width Half Maximum) of rocking shown in FIG. 3 represents a FWHM(Full Width Half Maximum) of rocking of the (111) plane, which indicatesbetter crystallinity, as the value thereof is smaller.

As shown in FIG. 3, when comparing between the specimens No. 1 to No. 4not added with Nb and the specimens No. 5 to No. 8 added with Nb, abetter crystallinity and a more uniform in-plane distribution areobtained in the specimens No. 5 to No. 8. The fact that the FWHM (FullWidth Half Maximum) of rocking becomes smaller by 0.4 degree indicatesthat the crystallinity has been improved remarkably.

In FIGS. 4A and 4B, the examination results of the nonlinear capacityand the electrostatic capacity are shown, respectively. In theexamination, after performing the above-mentioned examinations on thecrystallinity and the like, patterning of the top electrode film, theferroelectric film and the bottom electrode film was performed, andcapacity measurement of each specimen was carried out at 40 points inplane. In the measurement of the nonlinear capacity, the measuringvoltage was set at 0 V ±10 mV, while in the measurement of theelectrostatic capacity, the measuring voltage was set at 3 V ±10 mV. InFIGS. 4A and 4B, the maximum values and the minimum values are showntogether with the mean values (points shown by the lozenges). Thespecimen No. 9 shown in FIGS. 4A and 4B is a specimen in which a heattreatment time of 30 seconds on RTA was applied to the specimen No. 6.

As shown in FIGS. 4A and 4B, when comparing the specimens No. 1 and No.2 having the La content of 3.0 mol % with the specimens No. 3 and No. 4having 1.5 mol %, higher nonlinear capacity and higher electrostaticcapacity were obtained in the specimens No. 1 and No. 2. Also, whentaking notice of the Nb content, higher nonlinear capacity and higherelectrostatic capacity were obtained in the specimens having larger Nbcontents. Further, when taking notice of a ferroelectric film thickness,higher nonlinear capacity and higher electrostatic capacity wereobtained in the specimens No. 2, No. 4, No. 6, No. 8 and No. 9, eachhaving a thickness of 120 nm, than in the specimens No. 1, No. 3, No. 5and No. 7, each having a thickness of 150 nm.

Also, for each specimen, a hysteresis loop as shown in FIG. 15, whichindicates the relationship between an applied voltage and apolarization, was obtained, and a variety of values were obtained fromthe hysteresis loop. The results thereof are shown in FIGS. 5A, 5B and6. Here, the switching charge Q_(SW) is a value found from Formula 1shown below, using values P, U, N and D obtained from the hysteresisloop.

$\begin{matrix}{{Qsw} = \frac{\left( {P - U} \right) + \left( {N - D} \right)}{2}} & {{Formula}\mspace{20mu} 1}\end{matrix}$

When comparing the specimens No. 1 and No. 2 with the specimens No. 3and No. 4, as the La content was smaller, the value P became larger(FIG. 5A) and the value U became smaller (FIG. 5B). Also, when takingnotice of the Nb content, the specimen having a larger Nb content had asmaller value P (FIG. 5A) and had a larger value U (FIG. 5B). Here, whencomparing the specimens No. 3 and No. 4 having the Nb content of 0 mol %with the specimens No. 5 and No. 6 having 1 mol %, the differencebetween the values P and U was relatively small. Meanwhile, whencomparing the specimens No. 5 and No. 6 having the Nb content of 1 mol %with the specimens No. 7 and No. 8 having 4 mol %, the differencebetween the values P and U was relatively large. Further, when takingnotice of the ferroelectric film thickness, higher values P and U wereobtained in the specimens No. 2, No. 4, No. 6, No. 8 and No. 9 eachhaving a thin thickness.

Also, as shown in FIG. 6, when comparing the specimens No. 1 and No. 2with the specimens No. 3 and No. 4, in the specimens having smaller Lacontents, each switching charge Q_(SW) became higher. Also, when takingnotice of the Nb content, the specimen having a larger Nb content had asmaller switching charge Q_(SW). Here, when comparing the specimens No.3 and No. 4 having the Nb content of 0 mol % with the specimens No. 5and No. 6 having 1 mol %, the variation of a saturated switching charge(applied voltage: 3 V) was small, whereas the variation of the switchingcharge when the applied voltage was set at 1.8 V was large. Also, whencomparing the specimens No. 5 and No. 6 having the Nb content of 1 mol %with the specimens No. 7 and No. 8 having 4 mol %, there were a largesaturated switching charge and a large variation of the switching chargewhen the applied voltage was set at 1.8 V. Further, when taking noticeof the ferroelectric film thickness, in the specimens No. 2, No. 4, No.6, No. 8 and No. 9 having thin thickness, there was a large switchingcharge when the applied voltage was set at 1.8 V, whereas the saturatedswitching charge was small.

Also, on the occasion of the examination of the coercive voltage V_(C),after obtaining the relationship between the applied voltage and thevalue P, an applied voltage having the largest ratio of the variation ofthe value P to the variation of the applied voltage was determined asthe coercive voltage V_(C). The result thereof is shown in FIG. 7. Itshould be noted that the smaller the coercive voltage V_(C) is, thefaster the polarity reversal speed becomes.

As shown in FIG. 7, when comparing the specimens No. 1 and No. 2 withthe specimens No. 3 and No. 4, the smaller La content the specimen had,the smaller the coercive voltage V_(C) became. Also, when taking noticeof the Nb content, the smaller Nb content the specimen had, the smallerthe coercive voltage V_(C) became. Further, when taking notice of theferroelectric film thickness, in the specimens No. 2, No. 4, No. 6, No.8 and No. 9 having the thinner thickness, the coercive voltage V_(C)became the smaller.

Also, as shown in FIG. 8, when comparing the specimens No. 1 and No. 2with the specimens No. 3 and No. 4, the less La content the specimenhad, the larger the leak current became to a certain amount. Takingnotice of the Nb content, the more Nb content the specimen had, thesmaller the leak current became. Further, taking notice of theferroelectric film thickness, in the specimens No. 2, No. 4, No. 6, No.8 and No. 9 having the thinner thickness, the leak current became thelarger. Here, the applied voltage of “+5 V” indicates that the voltage“+5 V” was applied to the bottom electrode with a criterion of the topelectrode potential, while the applied voltage of “−5 V” indicates thatthe voltage “−5 V” was applied to the bottom electrode with a criterionof the top electrode potential.

As such, for example, when comparing the specimens No. 3 and No. 4including no Nb with the specimens No. 5 and No. 6 including Nb, bettercrystallinity and more uniform orientation were obtained in thespecimens No. 5 and No. 6, and also, the switching charge Q_(SW) becamelarger, and both the coercive voltage V_(C) and the leak current becamesmaller. It should be noted that, although the coercive voltage V_(C)and the leak current can be reduced by adding La and Nb, the more theaddition amount becomes, the smaller the switching charge becomes.Therefore, preferably, the addition of La and Nb is no greater than 5mol %, respectively, and more preferably, no greater than 4 mol %. Also,in the first test, there has been formed the ferroelectric film furtherincluding Sr and Ca as the donor elements in the A-site. Instead ofincluding the above Sr and Ca, the similar result may be obtained if Nbis included as the donor element in the B-site.

(Second Test)

In a second test, ferroelectric capacitors (discrete) each having asquare plane shape with side lengths of 50 μm were formed, and theelectric characteristics thereof were examined. Also, a memory cellarray having 1428 ferroelectric capacitors in number, each having arectangular plane shape with long-side lengths of 1.80 μm and short-sidelengths of 1.15 μm was formed, and the electric characteristics thereofwere examined. The examinations were performed after wirings wereformed. As ferroelectric films, (Pb,Ca,Sr) (Zr,Ti)O₃ films to which Laand Nb were added, were formed. The contents (mol %) of La and Nb in theferroelectric film of each specimen and the thickness (nm) of theferroelectric film are shown in Table 2.

TABLE 2 Specimens No. 11 No. 12 La 3 1.5 Nb 0 1 Thickness 150 150

As a kind of the electric characteristics, a hysteresis loop at the timeof applied voltage of 3 V was obtained, from which the switching chargeQ_(SW) and the differences (P−U) between the values P and U wereobtained. The results thereof are shown in FIGS. 9A and 9B. In FIG. 9A,the discrete result is shown, while in FIG. 9B, the result of the memorycell array is shown.

As shown in FIGS. 9A and 9B, when compared with the specimen No. 11, thespecimen No. 12 had increases of the switching charge Q_(SW) of about16% in the discrete, and of about 18% in the memory cell array. Thereason is that the content La is smaller in the specimen No. 12.

Also, as a kind of the electric characteristics, leak currents weremeasured. The results thereof are shown in FIGS. 10A and 10B. In FIG.10A, the discrete result is shown, while in FIG. 10B, the result of thememory cell array is shown.

As shown in FIGS. 10A and 10B, the leak currents came to the same orderin between the specimen No. 11 and the specimen No. 12. This resultmeans that, although the leak current will increase if the La content issimply lowered, the increase of the leak current was suppressed in thespecimen No. 12 because of inclusion of Nb. In other words, the additionof Nb canceled the decrease of La.

FIG. 11 shows a graph illustrating a relationship of the appliedvoltages to the switching charge Q_(SW) in the memory cell array. Themeasurement of polarization was performed at room temperature (24° C.)−45° C. and 90° C.

In regard to the switching charge Q_(SW) obtained in the measurement at−45° C., there was substantially no difference between the specimen No.11 and the specimen No. 12 under an applied voltage of 1.8 V or lower.In contrast, when the applied voltage came to 1.9 V or higher, theswitching charge Q_(SW) was increased more remarkably in the specimenNo. 12. Also, in regard to the switching charge Q_(SW) obtained in themeasurement at room temperature, at an applied voltage of 1.7 V orhigher, the switching charge Q_(SW) were increased more remarkably inthe specimen No. 12. Further, in regard to the switching charge Q_(SW)obtained in the measurement at 90° C., at an applied voltage of 1.0 V orhigher, the switching charge Q_(SW) was increased more remarkably in thespecimen No. 12. As such, in each measurement temperature, the switchingcharge Q_(SW) in the specimen No. 12 was larger than in the specimen No.11. The reason is that the content La is smaller in the specimen No. 12.

In FIG. 12, examination results with respect to the fatigue loss of thememory cell array are shown. In the examination, a readout voltage wasset at 3 V, a stress voltage was set at 7 V, and applications of voltagewere repeated for 2.0×10⁸ times.

A reduction rate (fatigue loss) of the switching charge Q_(SW) to theinitial value in the specimen No. 12 was 12.86%. In contrast, thereduction rate (fatigue loss) of the switching charge Q_(SW) to theinitial value in the specimen No. 11 was 13.56%. In case of decreasingthe La content, there is a probability of an increase in the fatigueloss. However, in the specimen No. 12, such the fatigue loss increasewas not produced because Nb was included.

In FIG. 13, examination results in regard to the thermal depolarizationin the memory cell array were shown. In the examination, writing wasperformed at room temperature, and when readout was performed at roomtemperature after being left intact under a variety of temperatures forone hour, the difference between the values P and U was obtained. Let avalue (P−U) obtained when reading out after left intact at roomtemperature be 100%, in the case of readout after left at 250° C., thevalue (P−U) was reduced to the order of 50% in the specimen No. 11,whereas the value (P−U) as high as 70% or of that order was obtained inthe specimen No. 12. In other words, the degree of thermaldepolarization was suppressed lower in the specimen No. 12. The reasonis considered that the Curie temperature of the specimen No. 12 is ashigh as about 360° C., in contrast to the Curie temperature of thespecimen No. 11 of about 340° C.

In FIGS. 14A and 14B, examination results on an imprint characteristicof the memory cell array are shown. In FIG. 14A, the relationshipbetween a heat treatment time and the value (P−U) is shown, while inFIG. 14B, an OS_RATE is shown. Here, in FIGS. 14A and 14B, the worstresults of each specimen are shown. The greater the value (P−U) is, thegreater the margin in the device becomes. Also, the smaller the absolutevalue of the OS_RATE is, the more hardly the imprint occurs. As shown inFIGS. 14A and 14B, there were obtained the results that, in the specimenNo. 12, the imprint is harder to occur, and a larger margin is secured,than in the specimen No. 11.

As such, as compared with the specimen No. 11, it is possible to obtaina higher switching charge Q_(SW) by the specimen No. 12, in which thethermal depolarization and the imprint were hard to occur. Also, thespecimen No. 12 produces a higher margin after the fatigue, and isendurable for use in a severer environment.

It should be noted that, although a planar-type ferroelectric capacitorhas been manufactured in the aforementioned embodiment, it may also bepossible to apply the present invention to a stack-type ferroelectriccapacitor. In this case, a portion of a contact plug such as a W plugconnected to a transistor such as a MOSFET is connected to the bottomelectrode of the ferroelectric capacitor. Also, when adopting thestack-type, high-temperature integrated etching may be performed.

Also, a crystal structure of the substance constituting theferroelectric film is not limited to the perovskite structure, but abismuth layer structured ferroelectrics may be applicable, for example.Further, the composition of the substance constituting the ferroelectricfilm is not particularly limited. For example, in the A-site, Pb (lead),Sr (strontium), Ca (calcium), Bi (bismuth), Ba (barium), Li (lithium)and/or Y (yttrium) may be included. Also, in the B-site, Ti (titan), Zr(zirconium), Hf (hafnium), V (vanadium), Ta tantalum), W (tungsten), Mn(manganese), Al (aluminum), Bi (bismuth) and/or Sr (strontium) may beincluded.

As chemical formulae of the substances constituting the ferroelectricfilm, for example, Pb(Zr,Ti)O₃, (Pb,Ca) (Zr,Ti)O₃, (Pb,Ca) (Zr,Ti,Ta)O₃,(Pb,Ca) (Zr,Ti,W)O₃, (Pb,Sr) (Zr,Ti)O₃, (Pb,Sr) (Zr,Ti,W)O₃, (Pb,Sr)(Zr,Ti,Ta)O₃, (Pb,Ca,Sr)(Zr,Ti)O₃, (Pb,Ca,Sr)(Zr,Ti,W)O₃, (Pb,Ca,Sr)(Zr,Ti,Ta)O₃, SrBi₂Ta₂O₉, Bi₄Ti₃O₉, and BaBi₂Ta₂O₉ may be listed, thoughit is not limited thereto. Also, Si may be added to the abovesubstances.

Also, the compositions of the top electrode and the bottom electrode arenot limited particularly. The bottom electrode may be configured of, forexample, Pt (platinum), Ir (iridium), Ru (ruthenium), Rh (rhodium), Re(rhenuim), Os (osmium) and/or Pd (palladium). It may also be possible tobe configured of the oxides thereof. The top electrode may be configuredof the oxides of Pt, Ir, Ru, Rh, Re, Os and/or Pd. Further, the topelectrode may be configured of a lamination of a plurality of films.

Further, the structure of the ferroelectric memory cell is not limitedto 1T1C type, but 2T2C type may be possible. Also, in the ferroelectricmemory, the ferroelectric capacitor itself may constitute both a memoryportion and a switching portion in common. In this case, the structuremay be such that the ferroelectric capacitor is formed in place of thegate electrode of a MOS transistor. Namely, a ferroelectric capacitor isformed on a semiconductor substrate by the intermediary of a gateinsulating film.

Also, a ferroelectric capacitor may be provided in a logic circuit orthe like. In this case, a DRAM having above-described ferroelectriccapacitor may be configured.

Further, there is no particular restriction on the method for formingthe ferroelectric film. For example, a sol-gel method, a metal organicdeposition (MOD) method, a CSD (chemical solution deposition) method, achemical vapor deposition (CVD) method, an epitaxial growth method, asputtering method, an MOCVD (metal organic chemical vapor deposition)method, or the like may be adopted.

INDUSTRIAL APPLICABILITY

As described above in detail, according to the present invention, it ispossible to improve the crystallinity of a ferroelectric film whileobtaining better uniformity. As a result, the characteristic of theferroelectric capacitor can be improved.

1. A semiconductor device comprising: a semiconductor substrate; and aferroelectric capacitor comprising: a ferroelectric film formed oversaid semiconductor substrate, said ferroelectric film being constitutedof a substance of which chemical formula is expressed by ABO₃, addedwith La and Nb; a first top electrode film formed on said ferroelectricfilm, said first top electrode film including an oxide of Ir, and asecond top electrode film formed on said first top electrode film, saidsecond top electrode film including Ir, wherein an oxygen composition ofsaid first top electrode film is smaller than that of said second topelectrode film.
 2. The semiconductor device according to claim 1,wherein a content of La in said ferroelectric film is 0.1 to 5 mol %. 3.The semiconductor device according to claim 1, wherein a content of Nbin said ferroelectric film is 0.1 to 5 mol %.
 4. The semiconductordevice according to claim 1, herein a content of La is 0.1 to 5 mol %and a content of Nb is 0.1 to 5 mol % in said ferroelectric film.
 5. Thesemiconductor device according to claim 1, wherein a crystal structureof said substance constituting said ferroelectric film is either aperovskite structure or a bismuth layer structured ferroelectrics. 6.The semiconductor device according to claim 1, wherein said substanceconstituting said ferroelectric film includes at least one kind ofelements selected from the group consisting of Pb, Sr, Ca, Bi, Ba, Liand Y, in the A-site.
 7. The semiconductor device according to claim 1,said substance constituting said ferroelectric film includes at leastone kind of elements selected from the group consisting of Ti, Zr, Hf,V, Ta, W, Mn, Al, Bi and Sr, in the B-site.
 8. The semiconductor deviceaccording to claim 1, wherein a chemical formula of said substanceconstituting said ferroelectric film is expressed by one kind selectedfrom the group consisting of: Pb(Zr,Ti)O₃, (Pb,Ca)(Zr,Ti)O₃,(Pb,Ca)(Zr,Ti,Ta)O₃, (Pb,Ca)(Zr,Ti,W)O₃, (Pb,Sr)(Zr,Ti)O₃,(Pb,Sr)(Zr,Ti,W)O₃, (Pb,Sr)(Zr,Ti,Ta)O₃, (Pb,Ca,Sr)(Zr,Ti)O₃,(Pb,Ca,Sr)(Zr,Ti,W)O₃, (Pb,Ca,Sr)(Zr,Ti,Ta)O₃, SrBi₂Ta₂O₉, Bi₄Ti₃O₉, andBaBi₂Ta₂O₉.
 9. The semiconductor device according to claim 8, wherein Siis further added to said substance constituting said ferroelectric film.10. The semiconductor device according to claim 1, wherein saidferroelectric capacitor comprises a bottom electrode including at leastone kind of elements selected from the group consisting of Pt, Ir, Ru,Rh, Re, Os and Pd.
 11. The semiconductor device according to claim 1,wherein said ferroelectric capacitor comprises a bottom electrodeincluding an oxide of at least one kind of elements selected from thegroup consisting of Pt, Ir, Ru, Rh, Re, Os and Pd.
 12. The semiconductordevice according to claim 1, further comprising a memory cell arrayhaving said ferroelectric capacitors in a plurality of numbers.
 13. Thesemiconductor device according to claim 12, wherein each memory cellconstituting said memory cell array comprises: said ferroelectriccapacitor as a memory portion; and a transistor connected to saidferroelectric capacitor as a switching portion.
 14. The semiconductordevice according to claim 12, wherein each memory cell constituting saidmemory cell array comprises said ferroelectric capacitor as a memoryportion and a switching portion.
 15. The semiconductor device accordingto claim 1, wherein the composition of the second top electrode film isoff the stoichiometric composition of the oxide of Ir.
 16. Amanufacturing method of a semiconductor device comprising the step of:forming a ferroelectric capacitor above a semiconductor substrate, saidferroelectric capacitor comprising a ferroelectric film, a first topelectrode film formed on said ferroelectric film, said first topelectrode film including an oxide of Ir, and a second top electrode filmformed on said first top electrode film, said second top electrode filmincluding Ir, wherein said ferroelectric film is constituted of asubstance of which chemical formula is expressed by ABO₃, added with Laand Nb, wherein an oxygen composition of said first top electrode filmis smaller than that of said second top electrode film.
 17. Themanufacturing method of a semiconductor device according to claim 16,wherein a content of La in said ferroelectric film is set at 0.1 to 5mol %.
 18. The manufacturing method of a semiconductor device accordingto claim 16, wherein a content of Nb in said ferroelectric film is setat 0.1 to 5 mol %.
 19. The manufacturing method of a semiconductordevice according to claim 16, wherein a content of La is set at 0.1 to 5mol %, and a content of Nb is set at 0.1 to 5 mol % in saidferroelectric film.
 20. The manufacturing method of a semiconductordevice according to claim 16, wherein the composition of the second topelectrode film is off the stoichiometric composition of the oxide of Ir.